A. Banerjee, R. Hezar, Lei Ding, N. Schemm, B. Haroun
{"title":"A 29.5 dBm class-E outphasing RF power amplifier with performance enhancement circuits in 45nm CMOS","authors":"A. Banerjee, R. Hezar, Lei Ding, N. Schemm, B. Haroun","doi":"10.1109/ESSCIRC.2014.6942123","DOIUrl":null,"url":null,"abstract":"A high efficiency class-E outphasing RF power amplifier is presented using a new passive combining circuit. A Power Enhancement Circuit (PEC) and an Efficiency Enhancement Circuit (EEC) are also proposed as part of the combiner that increase output power without violating reliability limits and improve efficiency at power back-off, respectively. The proposed power amplifier is designed in 45nm CMOS technology. Simulation results and measurement data are presented to demonstrate the performance of the proposed PA. The PA delivers 29.5 dBm peak output power at 2.4GHz with 46.76% drain efficiency at peak output power, 32.96% drain efficiency at 3 dB power back-off and 21.16% drain efficiency at 6 dB power back-off. Better than -50 dBc ACPR is obtained with 64-QAM LTE signal with 10MHz and 20MHz bandwidth. 21% average efficiency is obtained with LTE signal with 6 dB peak-to-average power ratio (PAPR).","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2014.6942123","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
A high efficiency class-E outphasing RF power amplifier is presented using a new passive combining circuit. A Power Enhancement Circuit (PEC) and an Efficiency Enhancement Circuit (EEC) are also proposed as part of the combiner that increase output power without violating reliability limits and improve efficiency at power back-off, respectively. The proposed power amplifier is designed in 45nm CMOS technology. Simulation results and measurement data are presented to demonstrate the performance of the proposed PA. The PA delivers 29.5 dBm peak output power at 2.4GHz with 46.76% drain efficiency at peak output power, 32.96% drain efficiency at 3 dB power back-off and 21.16% drain efficiency at 6 dB power back-off. Better than -50 dBc ACPR is obtained with 64-QAM LTE signal with 10MHz and 20MHz bandwidth. 21% average efficiency is obtained with LTE signal with 6 dB peak-to-average power ratio (PAPR).
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
