{"title":"Modeling node architectures","authors":"W. Giloi, C. Lindemann, S. Pletner","doi":"10.1109/MASCOT.1998.693699","DOIUrl":null,"url":null,"abstract":"This paper presents a modeling approach based on deterministic and stochastic Petri nets (DSPN) for analyzing the performance of node architectures for MIMD multiprocessor systems with distributed memory. DSPN are a numerically solvable modeling formalism with a graphical representation. The modeling approach supports design decisions for node architectures by providing quantitative results concerning processor and memory utilization for several design alternatives. To illustrate the proposed approach, DSPN of two node architectures are presented and employed for a comparative performance study.","PeriodicalId":272859,"journal":{"name":"Proceedings. Sixth International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (Cat. No.98TB100247)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. Sixth International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (Cat. No.98TB100247)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MASCOT.1998.693699","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents a modeling approach based on deterministic and stochastic Petri nets (DSPN) for analyzing the performance of node architectures for MIMD multiprocessor systems with distributed memory. DSPN are a numerically solvable modeling formalism with a graphical representation. The modeling approach supports design decisions for node architectures by providing quantitative results concerning processor and memory utilization for several design alternatives. To illustrate the proposed approach, DSPN of two node architectures are presented and employed for a comparative performance study.
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