An Area Cost Optimized Fast Parallel Label Assignment VLSI Architecture

Abstract

Connected components labeling is a commonly used procedure when performing image analysis and segmentation, as well as pattern recognition processing. The state-of-the-art approach, proposed by (S.-H. Yang et al., 2005), uses a parallel algorithm to achieve high speed operation. Based on it, an area and speed efficient VLSI architecture was designed. However, as the size of the input image increases, the area cost increases as well. This paper proposes an optimization for the method from (S.-H. Yang et al., 2005), achieving considerable area cost reduction, mainly when large images are considered. The area economy is accomplished by processing the input image in partitions of columns. This way, the higher the number of columns of the input image, the greater will be the area cost reduction.