A System Delay Monitor Exploiting Automatic Cell-Based Design Flow and Post-Silicon Calibration

Abstract

In this work, we present a low-overhead performance monitor which can emulate the maximum operational frequency of a target system by utilizing a delay chain so as to achieve efficient adaptive voltage control. The proposed monitor can be fully built by logic cells provided by general PDKs; thus, an automatic cell-based design flow can be used for its implementation. In addition, interconnect delay behaviors can also be imitated by exploiting wires which are automatically routed. In order to validate our concept, the proposed monitor is fabricated with a 65-nm Fully Depleted Silicon on Insulator (FD-SOI) technology. Real chip experiments reveal that the automated layout design can achieve the reasonable ability to delay emulation. Indeed, when the maximum operational frequency of a CNN accelerator is emulated, the proposed SDM achieved several percents of the performance tracking error. Also, its power overhead is only few percents.