Elias Teodoro da Silva, M. A. Wehrmeister, L. Becker, F. Wagner, C. Pereira
{"title":"Design exploration in HW/SW co-design of real-time object-oriented embedded systems: the scheduler object","authors":"Elias Teodoro da Silva, M. A. Wehrmeister, L. Becker, F. Wagner, C. Pereira","doi":"10.1109/WORDS.2005.25","DOIUrl":null,"url":null,"abstract":"This paper discusses a design flow for multithread object-oriented real-time applications, running on top of an embedded, platform-based, customizable Java processor, which is prototyped using affordable FPGAs. The proposed approach enforces design space exploration activities, taking into account aspects like temporal behavior, memory footprint, and power/energy consumption. A case study containing a task scheduler implementation as both software and hardware modules is presented. While both implementations are compatible with the developed program from an interface point of view, they lead to different timing and footprint requirements. Their evaluation in terms of memory occupation and number of FPGA logic cells is presented.","PeriodicalId":335355,"journal":{"name":"10th IEEE International Workshop on Object-Oriented Real-Time Dependable Systems","volume":"2011 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-02-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"10th IEEE International Workshop on Object-Oriented Real-Time Dependable Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WORDS.2005.25","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
This paper discusses a design flow for multithread object-oriented real-time applications, running on top of an embedded, platform-based, customizable Java processor, which is prototyped using affordable FPGAs. The proposed approach enforces design space exploration activities, taking into account aspects like temporal behavior, memory footprint, and power/energy consumption. A case study containing a task scheduler implementation as both software and hardware modules is presented. While both implementations are compatible with the developed program from an interface point of view, they lead to different timing and footprint requirements. Their evaluation in terms of memory occupation and number of FPGA logic cells is presented.