Design Aspects of 65-nm CMOS MMICs

Abstract

We present design aspects and techniques for millimeter-wave circuits implemented in 65-nm CMOS. Different transmission line topologies are discussed and measurement results for a conventional coplanar waveguide and slow-wave coplanar waveguide implemented in 65-nm CMOS are shown. The attenuation of the on-chip transmission lines can be reduced by using slow-wave coplanar waveguides. A 1-stage cascode amplifier in 65-nm CMOS employing inductors as matching elements is presented. On-chip interconnections of the amplifier are implemented and modeled using coplanar waveguides. The ground plane of the coplanar waveguide provides a good ground reference for the entire circuit.