Performance tradeoffs in digit-serial DSP systems

Abstract

This paper addresses performance tradeoffs in digit-serial arithmetic architectures for design of dedicated and programmable DSP systems. The advantages and the disadvantages of the digit-serial approach over the bit-parallel approach are discussed in terms of area, latency and power consumption. The addition and the multiplication are chosen for comparison. Digit-serial adders have a significant area advantage over bit-parallel adders. Digit-serial multipliers, however, have less area advantage due to the large number of feedback registers. In addition, critical paths of digit-serial multipliers cannot be reduced significantly compared to low-latency bit-parallel multipliers such as the Wallace tree multiplier. Quantitative performance tradeoffs in design of both programmable and dedicated DSP systems are considered. It is shown that the digit-serial arithmetic is not suitable for programmable DSPs. However, dedicated DSPs can be successfully implemented with the digit-serial arithmetic in limited silicon area.