Interlock delay time minimization and its impact on the high-voltage half-bridge DC/DC converter

Abstract

In DC/DC power converters, as in many other applications with inverter circuits, the interlock delay time between IGBT switching on and off in the opposite inverter arms is used to avoid a short circuit in a DC link. It is suggested by several handbooks that 20% of the half period should be used. However, in some applications, e.g. power supplies with extended input voltage variations, much smaller interlock delay time must be used to ensure correct operation of the inverter. In this paper the interlock delay time minimization possibility is analyzed on an example of an existing experimental device based on 6.5 kV IGBTs. Moreover, the possible impact of interlock delay time minimization on the isolated DC/DC converter components, operability and efficiency is evaluated.