Evaluating FPGA Routing Architectures with Complex Grid Layouts

Abstract

The problem of FPGA architecture routability evaluation has always attracted the designers' attention. Nowadays most of the chip delay and area is due to the routing wires and switches that make accurate and efficient evaluation very important. Traditionally FPGA routing architectures have been studied using experimental techniques. However, a full CAD flow is time-consuming and requires tuning to a given architecture. Therefore, more attention is paid to various metrics, models and algorithms that allow routing evaluation without using a full design flow.Wotan is a modern tool that allows the designers to quickly estimate architectures’ routability. It evaluates the wires’ congestion and routability by counting paths in the routing graph. In this work we present further development of Wotan, adding support for complex grid layouts containing large macroblocks like RAM, etc. We show that the enhanced Wotan produce more accurate routability metric compared to the previous version.