A Novel VLSI Divide and Conquer Implementation of the Iterative Array Multiplier

Abstract

A novel VLSI architecture for binary multipliers is introduced. It is based on an existing parameterized divide and conquer algorithm that uses optimal partitioning and redundancy removal for simultaneous computation of partial sums. The VLSI implementation of the proposed parameterized binary multiplier architecture (PBMA) is obtained by applying this algorithm to the iterative array multiplier implementation. Two variations of the PBMA, namely PBMA-A and PBMA-AT, are implemented and compared to the conventional carry-save array multiplier implementation. For the 128-bit by 128-bit case, the area (A) optimized PBMA-A is shown to achieve significant area (A) savings of 57%, at the cost of18% increase in operational delay (T), while the area-time product (AT) optimized PBMA-AT is shown to achieve significant AT savings of 59%, reflecting area (A) and operational delay (T) savings of 46% and 24%, respectively