A scalability study of interconnect architectures for System-on-Chip

Abstract

Network-on-Chip (NoC) architectures were proposed to solve scalability issues experienced in bus-based SoCs. They incorporate a communication infrastructure defined by topology, routers and switches, in order to provide a scalable and high performance network for the SoC resources while satisfying the constraints of embedded platforms. The choice of appropriate NoC topology depends on the desired network size for the required performance. Simulation of NoCs based on real application traffic is time consuming, and therefore not a feasible approach for rapid design space exploration. In this paper, a methodology to study the scalability of three on-chip interconnect architectures, WK-recursive, Mesh and Spidergon, is presented. Simulation results are presented for different cases, demonstrating the potential of our approach for selecting the most scalable on-chip interconnect architecture.