Parameterized function unit library for methodology of integrating high level synthesis and floor plan

Abstract

Nowadays, in the domain of integrated circuit designing, delay and power on interconnect wires have been playing a dominant role in total performance of circuit. As a result, design closure problem comes out. To solve the problem, methodology of integrating high level synthesis and floorplanning becomes one of the focuses of recent researches. Function unit library is an important part of high level synthesis, so we have designed a special parameterized function unit library for integrating high level synthesis and floorplanning based on the traditional library. The new library has a special 4-level function unit model, contains more information of function unit, and is able to generate parameters for new function units