Analysis Of The Controllability Of A Sub-Micron CMOS Process Using TCAD

Abstract

In this paper we describe the statistical simulation and SPICE model prediction of a 0.8um CMOS process. The simulation environment consisted of an integrated TCAD framework combining two dimensional process and device simulation with physically-based SPICE model extraction. In-line process tolerances were assigned, and Monte Carlo simulation was used to predict the variation of device performance and worst case SPICE model parameters. The device parameter distributions resulting from 100 Monte Carlo simulations were found on average to match the three sigma limites of the electrical database within 5% as shown in Table 1. Nominal BSIM models extracted deterministically with pdFab were found to match the typical results of a proprietary device model within 10%.