Low power floating point MAFs-a comparative study

Abstract

We present a comparative study of three data path architectures for floating point multiply-accumulate fusion. Power/delay behavior of two new MAFs are compared with that of a modified IBM MAF. The functional partitioning of the new MAFs into four distinct, clock gated modules allows activity reduction. The switching activity function of the new MAFs is represented as a four state FSM. During any given operation cycle, only one of the data path modules is active, during which occasion, the logic assertion status of the circuit nodes of the other modules are maintained at their previous states. Critical path delay and latency are reduced by incorporating speculative rounding and data path simplifications. The new MAFs offer worst case power reductions in excess of 15% with FPGA realization while the corresponding figure for 0.35 micron CMOS process is better than 26%.