A flexible filter-based Mobile-to-Mobile Double Rayleigh Fading channel emulator

Abstract

A low-complexity and high performance configurable Double Rayleigh Mobile-to-Mobile fading channel emulator is proposed as well as its High Level Synthesis. The design and implementation of the proposed architecture based on a variant of the white Gaussian noise filtering method uses a minor hardware resource. The designed system is modeled using C/C++ high level language. Then the synthesis task into a Field-Programmable Gate Arrays (FPGA) is performed using Vivado 2014.2 High-Level Synthesis tool. Implementation results into a Xilinx Zynq-7 ZC706 xc7z045ffg900-2 FPGA shows that the proposed architecture uses only 1.5% of the configurable slices, 3% of the dedicated DSP48E, 4 BlockRAMs and it can generate up to 115 million fading samples per second. The analysis of the theoretical curves compared with the simulated one, in terms first order statistical properties of a double Rayleigh mobile-to-mobile fading channel, shows that there is a good agreement between the simulated results and the theoretical curves.