An Adaptive and Selective Instruction Active Push Mechanism for Multi-core Architecture

Abstract

Correct and effective instruction pre-fetch strategy is key technique to avoid instruction misses. Unfortunately, branch direction correctness and the accuracy of instruction pre-fetch is not very good, and the utilization ratio of memory bandwidth is relative low, all of these mentioned reasons are the main factors leading to instruction miss. This paper proposes an adaptive and selective instruction active push mechanism for multi-core architecture, called ASIAP. On one hand, request number of invalid instruction pre-fetch is decreased and precise instruction pre-fetch is carried on; on the other hand, part of non-sequential type requests are responded preferentially by a specific instruction active push unit adaptively and selectively. Simulation result indicates that, in double-core configuration, relative to three other strategies, Next_Line, Target_Line and Wrong_Path, the accuracy of ASIAP improves average 22.59%, 11.84% and 8.85% respectively. Relative to Next_Line, the reduction of L1 I-Cache miss ranges from 17.7% to 33.5%, average 26.08%.