J. Ayala, David Atienza Alonso, M. López-Vallejo, J. Mendias, R. Hermida, C. López-Barrio
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引用次数: 2
Abstract
In this paper, we introduce a new hardware/software approach to reduce the energy of the shared register file in upcoming embedded architectures with several VLIW processors. This paper includes a set of architectural extensions and special loop unrolling techniques for the compilers of MPSoC platforms. This complete hardware/software support enables reducing the energy consumed in the register file of MPSoC architectures up to a 60% without introducing performance penalties.
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