A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM4 Receiver with a -8-dB JTRAN 40-MHz 0.2-UIPP JTOL Clock and Data Recovery

Abstract

This paper presents a source-synchronous 60-Gb/s quarter-rate (1/4-rate) PAM4 receiver (Rx) with a jitter compensation clock and data recovery circuit (JCCDR) to overcome the stringent trade-off between jitter transfer (JTRAN) and jitter tolerance bandwidth (JTOL BW). The jitter compensation circuit (JCC) utilizes the delay-locked loop (DLL) filter voltage to produce a complementary control signal VLFINV, which modulates a group of complementary voltage-controlled delay lines (C-VCDL) so to negate the JTRANs on the recovered data and clock signals. The proposed 40-nm CMOS Rx test chip achieves error-free operation with PAM4 input from 30 to 60 Gb/s. The JCCDR achieves a 40-MHz JTOL BW with over 0.2-UIPP jitter amplitude while maintaining a -8-dB JTRAN. A jitter compensation ratio of around 60% has been achieved up to 40 MHz.