Behavioural Modelling and Simulation of Dual Cascaded PLL Based Frequency Synthesizer

Abstract

In this paper, behavioural model of a dual cascaded phase locked loop (PLL) based frequency synthesizer is presented and the results are validated through SystemVision simulation using very high speed Integrated circuit hardware description language-analog mixed signal (VHDL-AMS). Dual cascaded PLL consists of a low jitter PLL employing a voltage controlled crystal oscillator (VCXO) followed by a wideband PLL employing normal voltage controlled oscillator (VCO). The advantage of using dual PLL in cascade configuration is that it provides very good performance in terms of low jitter as compared to a single PLL based frequency synthesizer. Simulation results obtained are in good agreement with the theoretical calculations.