Low-Power and High Speed SRAM for Ultra Low Power Applications

Abstract

The rapid development of battery-powered gadgets has made low-power design a priority in recent years. In addition, integrated SRAM units in contemporary soCs have become an essential component. The increased number of transistors in SRAM units and the increased leakage in scaled technology of the MOS transistors have turned the SRAM unit into a power block from dynamic and static perspectives. This memory circuitry consumes many chips and determines the system’s overall power consumption. Typically, the primary 6T SRAM cell gives more power loss and delay. In this paper, various SRAM transistor cells have been built and analyzed from different topologies. A proposed low-power 9T SRAM cell area has improved reading and writing access time. As anticipated from the modeling findings, experimental results show a significant overall power decrease compared to traditional and previously published.