Synthesize pass transistor logic gate by using free binary decision diagram

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI:10.1109/ASIC.1997.617005

M. Tachibana

引用次数: 6

Abstract

In this paper, a heuristic algorithm for free BDD node minimization is presented. This algorithm is designed to minimize small size FBDDs with application to synthesize pass transistor logic gate families. Experimental results based on 169 single output functions from MCNC benchmark two-level logic examples indicate 22 to 24% reduction of node count compared with initial ROBDD. Also, experimental results based on HWB functions (N=3-16) indicate node count reduced to 30 to 40% larger than the theoretical limit.

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利用自由二进制决策图合成通型晶体管逻辑门

本文提出了一种自由BDD节点最小化的启发式算法。该算法设计用于最小化小尺寸fbdd，并应用于通管逻辑门系列的合成。基于MCNC基准两级逻辑示例的169个单输出函数的实验结果表明，与初始ROBDD相比，节点数减少了22 ~ 24%。此外，基于HWB函数(N=3-16)的实验结果表明，节点数比理论极限减少了30 - 40%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)

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