High Speed Efficient Multiplier Design using Reversible Gates

Abstract

Now-$a$-days, reversible logic is getting huge interest among the IC designer because it consumes less power. Reversible logic has been found in applications like Digital signal processing, DNA and quantum computing and high speed VLSI design. The implementation of reversible logic contains number of reversible logic gates. In this work, a multiplier is designed using HNG gate. An efficient high speed multiplier has been proposed using verilog coding and Cadence 180 nm technology is used for its implementation. Compared to the existing multiplier, the proposed multiplier consumes less power and comparatively less quantum cost. Hence, the proposed multiplier results in less power consumption without sacrificing the speed.