Design of Dynamically Reconfigurable Processor for the H.264/AVC Image Prediction and De-blocking Filter

Abstract

H.264/AVC provides high video quality at substantially low bit rates. However, the computational complexity of H.264/AVC is very high. A high-speed general-purpose processor is necessary to process H.264/AVC. However, it is difficult to use such a processor for a portable device. Therefore, an application-specific processor is necessary. A dynamic reconfiguration can virtually expand the circuit area in a limited chip area. Therefore, this article proposes a dynamically reconfigurable processor for H.264/AVC image prediction. H.264/AVC contains inter-prediction processes and de-blocking filter. The inter-prediction processes and de-blocking filter are not used at the same time. The proposed processor was designed and synthesized, and dynamically reconfigures those circuits. As a result, look up tables (LUTs) were reduced 10%, flip-flops were about the same, and the maximum delay was increased 10%.