A software-defined hybrid cache with reduced energy: poster

Abstract

Energy becomes an inevitable challenge when using a large die-stacking DRAM cache as part of memory. Emerging volatile STT-RAM can be integrated with DRAM as a software-managed hybrid cache to effectively reduce the static and dynamic energy of large cache, but there is extra refresh energy overhead. We observe that reducing the refresh rate of volatile STT-RAM will provide significant energy savings while introducing a small number of bit errors that can be easily tolerated by most error-resilient applications. Thus, we propose a quality-aware approximate die-stacking hybrid cache and develop a novel data allocation scheme. We also propose the online quality monitor and the light-weight check scheme for error recovery. The results show an average 91% reduction in volatile STT-RAM refresh energy with minimal loss in output quality.