Efficient DFA-Resistant AES Hardware Based on Concurrent Fault Detection Scheme

Abstract

This paper presents an efficient AES encryption/decryption hardware architecture with a fault detection scheme. The proposed hardware detects faults during encryption and decryption immediately to counter fault injection attacks such as differential fault analysis (DFA). The proposed hardware employs a fault detection scheme to verify the computation correctness and detect faults, where the datapath is divided into two sub-blocks of linear and nonlinear parts. An inverse function is executed one clock cycle after a half-of-round function. The hardware combines the proposed fault detection scheme with state-of-the-art datapath optimization techniques to achieve both efficient AES encryption/decryption and resistance to DFA. We showed through logic synthesis and simulation that the proposed AES hardware achieves 92% higher area-throughput efficiency and 47% lower power consumption than conventional hardware.