A Potential Solutions-Based Parallelized GA for Application Graph Mapping in Reconfigurable Hardware

Abstract

High-performance computing systems including Reconfigurable Hardware (RH) such as Field Programmable Gate Array (FPGA) proved a significant impact on the speed of application execution with useful reconfiguration and parallelism attributes. To make one application executable on RH, it is required to perform some heavy computational compilation preprocessing phases. In this paper, we aim to reduce compilation overhead in the NP-hard problem of the mapping phase by utilizing a novel Parallelized Genetic Algorithm (PGA) which is based on potential solutions in the search space. In the search space of possible solutions, we analytically separate weak and potential solutions to guide the GA for reaching the optimal solution faster. Moreover, this separation has been carried out independently to add parallelism into our GA and also, to switch between search spaces for keeping the generalization of GA exploration. Comparison results showed that our approach could make a considerable gap at the starting points of solution searching and therefore, found the optimal solution in a more reasonable time.