Compiler orchestrated prefetching via speculation and predication

ASPLOS XI Pub Date : 2004-10-07 DOI:10.1145/1024393.1024416
R. Rabbah, Hariharan Sandanagobalane, M. Ekpanyapong, W. Wong
{"title":"Compiler orchestrated prefetching via speculation and predication","authors":"R. Rabbah, Hariharan Sandanagobalane, M. Ekpanyapong, W. Wong","doi":"10.1145/1024393.1024416","DOIUrl":null,"url":null,"abstract":"This paper introduces a compiler orchestrated prefetching system as a unified framework geared toward ameliorating the gap between processing speeds and memory access latencies. We focus the scope of the optimization on specific subsets of the program dependence graph that succinctly characterize the memory access pattern of both regular array-based applications and irregular pointer-intensive programs. We illustrate how program embedded precomputation via speculative execution can accurately predict and effectively prefetch future memory references with negligible overhead. The proposed techniques reduce the total running time of seven SPEC benchmarks and two OLDEN benchmarks by 27% on an Itanium 2 processor. The improvements are in addition to several state-of-the-art optimizations including software pipelining and data prefetching. In addition, we use cycle-accurate simulations to identify important and lightweight architectural innovations that further mitigate the memory system bottleneck. In particular, we focus on the notoriously challenging class of pointer-chasing applications, and demonstrate how they may benefit from a novel scheme of it sentineled prefetching. Our results for twelve SPEC benchmarks demonstrate that 45% of the processor stalls that are caused by the memory system are avoidable. The techniques in this paper can effectively mask long memory latencies with little instruction overhead, and can readily contribute to the performance of processors today.","PeriodicalId":344295,"journal":{"name":"ASPLOS XI","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"50","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ASPLOS XI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1024393.1024416","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 50

Abstract

This paper introduces a compiler orchestrated prefetching system as a unified framework geared toward ameliorating the gap between processing speeds and memory access latencies. We focus the scope of the optimization on specific subsets of the program dependence graph that succinctly characterize the memory access pattern of both regular array-based applications and irregular pointer-intensive programs. We illustrate how program embedded precomputation via speculative execution can accurately predict and effectively prefetch future memory references with negligible overhead. The proposed techniques reduce the total running time of seven SPEC benchmarks and two OLDEN benchmarks by 27% on an Itanium 2 processor. The improvements are in addition to several state-of-the-art optimizations including software pipelining and data prefetching. In addition, we use cycle-accurate simulations to identify important and lightweight architectural innovations that further mitigate the memory system bottleneck. In particular, we focus on the notoriously challenging class of pointer-chasing applications, and demonstrate how they may benefit from a novel scheme of it sentineled prefetching. Our results for twelve SPEC benchmarks demonstrate that 45% of the processor stalls that are caused by the memory system are avoidable. The techniques in this paper can effectively mask long memory latencies with little instruction overhead, and can readily contribute to the performance of processors today.
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编译器通过推测和预测编排预取
本文介绍了一个编译器编排的预取系统,作为一个统一的框架,旨在改善处理速度和内存访问延迟之间的差距。我们将优化的范围集中在程序依赖图的特定子集上,这些子集简洁地描述了常规基于数组的应用程序和不规则指针密集型程序的内存访问模式。我们说明了通过推测执行的程序嵌入式预计算如何能够准确地预测和有效地预取未来的内存引用,而开销可以忽略不计。所提出的技术在Itanium 2处理器上将七个SPEC基准测试和两个OLDEN基准测试的总运行时间减少了27%。除了这些改进之外,还有一些最先进的优化,包括软件流水线和数据预取。此外,我们使用周期精确的模拟来识别重要和轻量级的架构创新,从而进一步缓解内存系统瓶颈。特别地,我们将关注指针跟踪应用程序中最具挑战性的一类,并演示它们如何从一种新的指针哨兵预取方案中受益。我们对12个SPEC基准测试的结果表明,由内存系统引起的45%的处理器停滞是可以避免的。本文中的技术可以用很少的指令开销有效地掩盖长内存延迟,并且可以很容易地提高当今处理器的性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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