{"title":"Overcoming bottlenecks in high-speed transport systems","authors":"M. Siegel, Mark Williams, G. Rößler","doi":"10.1109/LCN.1991.208092","DOIUrl":null,"url":null,"abstract":"An architecture is presented for HSLAN/MAN controllers. This front-end processor system (FEP) is designed for operation in a CLN/LLC 1 environment, and implements the ISO OSI TP4 transport protocol. The FEP uses one or more commercial microprocessors with layers 2b-4 implemented in firmware. The protocol processors are supported by custom VLSI hardware such as a checksummer, DMA units, and process coupling devices as required. Layers 1 and 2a are provided by commercial chipsets. The FEP is optimised for a LAN/MAN environment while allowing the host to communicate over wide-area networks. It is general enough to be adapted to non-OSI protocol suites. Initial estimates indicate that the FEP should be able to transmit and receive at full FDDI bandwidth with a TPDU length of 1k octets.<<ETX>>","PeriodicalId":163373,"journal":{"name":"[1991] Proceedings 16th Conference on Local Computer Networks","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991] Proceedings 16th Conference on Local Computer Networks","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LCN.1991.208092","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12
Abstract
An architecture is presented for HSLAN/MAN controllers. This front-end processor system (FEP) is designed for operation in a CLN/LLC 1 environment, and implements the ISO OSI TP4 transport protocol. The FEP uses one or more commercial microprocessors with layers 2b-4 implemented in firmware. The protocol processors are supported by custom VLSI hardware such as a checksummer, DMA units, and process coupling devices as required. Layers 1 and 2a are provided by commercial chipsets. The FEP is optimised for a LAN/MAN environment while allowing the host to communicate over wide-area networks. It is general enough to be adapted to non-OSI protocol suites. Initial estimates indicate that the FEP should be able to transmit and receive at full FDDI bandwidth with a TPDU length of 1k octets.<>
提出了一种HSLAN/MAN控制器的体系结构。该前端处理器系统(FEP)是为在CLN/LLC 1环境下运行而设计的，并实现了ISO OSI TP4传输协议。FEP使用一个或多个商业微处理器，在固件中实现层2b-4。协议处理器由自定义VLSI硬件(如checksummer、DMA单元和所需的进程耦合设备)支持。1层和2a层由商用芯片组提供。FEP针对LAN/MAN环境进行了优化，同时允许主机在广域网上通信。它足够通用，可以适应非osi协议套件。初步估计表明，FEP应该能够以全FDDI带宽发送和接收，TPDU长度为1k字节
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