Parametric hierarchical mesh interconnected structure for Network-on-Chip

Abstract

With the integration of cores increasing, the on-chip-network (NoC) latency and the throughput are getting worse in traditional structures. This paper proposed a novel parameter-based on the hierarchical mesh interconnected NoC (PHMNoC) to improve the integration and performance. We use structural parameters and cross-layer threshold parameter to achieve scalability for different system size and balance traffic load among layers respectively. Experimental results demonstrated that PHMNoC had lower latency and higher throughput than conventional 2D mesh and hierarchical NoC such as Concentrated-Mesh and Cluster-Hierarchical-Mesh in different size systems, while the increasement of resources overhead was modest.