Algorithms for synthesis and average distribution of variable sized MOS components for efficient Analog VLSI devices

Abstract

In the field of Analog VLSI layout design, large variation of MOS component sizes causes mismatches and reduces the performance and splitting is necessary to reduce the variation. On the other hand, intensity of imposing always varies during fabrication. In this ongoing research, the solutions of above problems are introduced with some algorithm implementations. Two different sizes of components can be split into optimized number of pieces and an algorithm distributes them in an average and symmetrical (better) arrangement such that it can ensure average imposing and the efficiency increases. The computer generated solutions are compared with other possible solutions and proved better.