High voltage isolation silicon node wafer saw

Abstract

Texas Instruments' high voltage isolation semiconductor devices enable safe transmission of data and power between high voltage and low voltage circuits in modern electrical systems. The silicon technology for isolation contains higher metallization content in the wafer saw street and therefore, requires the assembly dicing process window to be well characterized to enable robust manufacturing and quality. This paper provides an overview of mechanisms that induce top side and flipside silicon chipping, analyzes the impact of metal density in wafer saw street on chipping severity, and discusses the attributes in mechanical saw process that can be characterized to prevent chipping defects in high volume manufacturing.