A novel approach to estimate the impact of analog circuit performance based on the small signal model under process variations

Abstract

Continuous scaling in CMOS fabrication process makes integrated circuits more vulnerable to process variations. The impact on circuit performance caused by process variations in CMOS circuit is usually analyzed by Monte Carlo method with a large number of simulation runs. This paper proposes a novel approach to estimate the impact of analog circuit performance based on the small signal model under process variations. The accuracy of the small signal model has been verified with CMOS circuit. The proposed approach has been demonstrated by a CMOS two-stage operational transconductance amplifier (OTA). To achieve an accurate estimate, the modified small signal model which consider more parasitic capacitors in CMOS transistor, has been applied in the proposed approach. By applying the proposed approach based on optimization method, the upper and lower bounds of magnitude and phase, can be evaluated accurately in much less computation time compared to Monte Carlo simulations. All experimental results are carried out using a standard 0.35-µm CMOS process technology.