Dual Code Compression for Embedded Systems

Abstract

Computer architects aim to make embedded systems more powerful and space efficient. Code compression is traditionally used to reduce the code size by compressing the instructions with higher static frequency. However, it may introduce decompression overhead. Performance-aware compression techniques try to improve performance through reduction of cache misses by utilizing the dynamic instruction frequency, but it sacrifices code size. We propose a dual compression scheme that aims to simultaneously optimize both code size reduction and performance improvement. Experimental results show that our approach can simultaneously achieve best of both scenarios - achieves up to 40% compression efficiency and an average performance improvement of 50%.