Stephen A. Mancini, Seung Yup Jang, Dongyoung Kim, Woongje Sung
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引用次数: 0
Abstract
Several different designs of 1.2kV-rated 4H-SiC JBS diode integrated MOSFETs (JBSFETs) have been successfully fabricated to increase the 3rd quadrant device performance while maintaining the electrical characteristics on both the forward and blocking modes of operation when compared to its MOSFET counterpart. Incorporating the Schottky area in an efficient manner to improve overall device performance has been a critical path in the development and adoption of 4H-SiC JBSFETs rather than MOSFETs co-packaged with JBS Diodes. Device design, fabrication, and electrical performances are discussed in this paper and as a result, an optimum JBSFET design is proposed.
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