Binary decision diagram optimization method based on multiplexer reduction methods

Abstract

In VLSI circuit synthesis, multiplexers are widely used as a basic building element because of their ability to perform any Boolean function. Since multiplexers form a significant part of total circuit area, designers often focus on application of various optimizations. Multiplexer optimization techniques result in significant improvement in performance, area and power consumption of synthetized VLSI circuits. One of such approaches is the use of BDD as a structural representation of a multiplexer tree along with BDD optimization methods. We proposed a novel BDD optimization algorithm combining residual variable with basic BDD reduction methods. Experimental results show that implemented algorithm reduces total amount of multiplexers in optimized multiplexer tree by a minimum of 74.19% compared to a non-optimized multiplexer tree. The residual variable method provides approximately 50% reduction, what is further improved by up to additional 17.65% using basic BDD optimization methods.