Design of a 20-GHz Phased-Array Receiver with high-precision Gain and Phase Control in 65nm CMOS

Abstract

This paper describes the design of a 20-GHz phased-array receiver based on 65nm CMOS. 6-bit phase control and 6-bit gain control are implemented by a passive vector-sum phase shifter with transformer-based compact quadrature generator and programmable gain amplifiers, moreover automatic state-selecting program is employed to realize high-precision phase/gain control. The simulated results indicate that the receiver achieve 29-32 dB gain and better than 2.9 dB noise figure in the frequency range of 18-23 GHz. 1.8 degree RMS phase error and 0.45 dB RMS gain error are obtained for phase control, 0.16 dB RMS gain error and 1.1 degree phase error are obtained for gain control. It is indicated that excellent phase and gain control performances are demonstrated.