{"title":"A low-cost SoC architecture for the next-generation home-networked set-top box","authors":"S. Ryan, A. Jones, R. Deaves","doi":"10.1109/ICCE.2009.5012370","DOIUrl":null,"url":null,"abstract":"This paper presents an SoC architecture which integrates 1500DMIPS of CPU processing resource and an optimized memory system in order to meet the high performance, low power and low cost requirements of next-generation set-top boxes.","PeriodicalId":154986,"journal":{"name":"2009 Digest of Technical Papers International Conference on Consumer Electronics","volume":"58 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 Digest of Technical Papers International Conference on Consumer Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCE.2009.5012370","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents an SoC architecture which integrates 1500DMIPS of CPU processing resource and an optimized memory system in order to meet the high performance, low power and low cost requirements of next-generation set-top boxes.
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