Implementation of a fixed-point 2D Gaussian Filter for Image Processing based on FPGA

Abstract

One of the very useful techniques in Image Processing is the 2D Gaussian Filter, especially when smoothing images. However, the implementation of a 2D Gaussian Filter requires heavy computational resources, and when it comes down to real-time applications, efficiency in the implementation is vital. Floating-point math represents an obstacle for this, as its implementation requires a large amount of computational power in order to achieve real-time image processing. On the other hand, a fixed-point approach is much more suitable; implementation of a 2D Gaussian Filter in FPGA using fixed-point arithmetic provides efficiency in the processing and reduction in computational costs. The purpose of this study is to present the FPGA resource usage for different sizes of Gaussian Kernel; to provide a comparison between fixed-point and floating point implementations; and to define the amount of bits are necessary to use in order to have a Root Mean Square Error (RMSE) below 5%.