{"title":"Fixed-point arithmetic error analysis of sparse LU decomposition on FPGAs","authors":"M. S. Feali, A. Ahmadi, A. Hamidi, M. Ahmadi","doi":"10.1109/ISSCS.2017.8034900","DOIUrl":null,"url":null,"abstract":"FPGAs are becoming an attractive platform for accelerating many computations including scientific applications. These applications demand high performance and high precision arithmetic. Decomposition of a matrix into lower and upper triangular matrices (LU decomposition) is a vital part of many scientific and engineering applications. This paper evaluates the accuracy of a fixed-point LU decomposition based on FPGA. Fixed-point architecture of LU decomposition is implemented on FPGA. Then several matrices with different sizes and random elements are decomposed using this architecture by various word-lengths. Using random matrices and different word-lengths, descriptive analysis of error is performed.","PeriodicalId":338255,"journal":{"name":"2017 International Symposium on Signals, Circuits and Systems (ISSCS)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International Symposium on Signals, Circuits and Systems (ISSCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCS.2017.8034900","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
FPGAs are becoming an attractive platform for accelerating many computations including scientific applications. These applications demand high performance and high precision arithmetic. Decomposition of a matrix into lower and upper triangular matrices (LU decomposition) is a vital part of many scientific and engineering applications. This paper evaluates the accuracy of a fixed-point LU decomposition based on FPGA. Fixed-point architecture of LU decomposition is implemented on FPGA. Then several matrices with different sizes and random elements are decomposed using this architecture by various word-lengths. Using random matrices and different word-lengths, descriptive analysis of error is performed.