Design and implementation of a ultra-high timing resolution pulse generator based on real-time computation

Hanglin Liu, Hongliang Chen, Zaiming Fu, Shirui Qi, Yindong Xiao, Houjun Wang
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引用次数: 3

Abstract

In the field of automatic test systems, direct digital synthesis (DDS) technology plays a crucial role with features such as fast frequency switching speed, high-frequency resolution, and flexible waveforms. However, the timing resolution of the pulse waveform generated by DDS technology is limited by the storage depth of waveform memory and sampling rate. DDS generates a maximum 1 clock cycle jitter in the pulse waveform as the frequency tune word (FTW) changes driven by the sampling clock, and the pulse width modulation (PWM) of the pulse waveform is not possible with DDS technology. In this paper, a parallel pulse waveform synthesis method based on real-time computation is proposed. The pulse waveform generated by this method has a timing resolution that far exceeds the sampling period including rising time resolution, falling time resolution, pulse width resolution, and delay resolution. Since the pulse parameters such as rising time, falling time, and pulse width can be independently adjusted with phase continuity, and the waveform samples are generated by real-time computation, the method can easily implement PWM and various modulations. The waveform samples computed in real-time correspond precisely to their theoretical phases with extremely low phase truncation error, thus jitter is greatly reduced and the timing resolution can be significantly improved. In this paper, based on the real-time computation of waveform samples, the sampling rate is increased eight times by parallelizing the computation. Each computing channel is run at 156.25 MHz, and the sampling rate of 1.25 GSPS waveform samples is achieved by running in parallel with eight channels. Finally, the pulse waveform is generated with a timing resolution of 0.2 ps, which theoretically requires a sampling rate of 5 TSPS to achieve.
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基于实时计算的超高时序分辨率脉冲发生器的设计与实现
在自动测试系统领域,直接数字合成(DDS)技术以其切换频率快、高频分辨率高、波形灵活等特点发挥着至关重要的作用。然而,DDS技术产生的脉冲波形的时序分辨率受到波形存储器的存储深度和采样率的限制。由于采样时钟驱动的频率调谐字(FTW)变化,DDS在脉冲波形中产生最大1个时钟周期的抖动,并且DDS技术无法实现脉冲波形的脉宽调制(PWM)。本文提出了一种基于实时计算的并行脉冲波形合成方法。该方法产生的脉冲波形具有远远超过采样周期的时序分辨率,包括上升时间分辨率、下降时间分辨率、脉宽分辨率和延迟分辨率。由于脉冲的上升时间、下降时间、脉宽等参数可以独立地进行相位连续调节,并且波形样本是通过实时计算生成的,因此该方法可以方便地实现PWM和各种调制。实时计算的波形样本与理论相位精确对应,相位截断误差极低,从而大大降低了抖动,显著提高了时序分辨率。本文在波形采样实时计算的基础上,通过并行化计算,将采样率提高了8倍。每个计算通道运行频率为156.25 MHz,通过8个通道并行运行实现1.25 GSPS波形采样率。最后生成时序分辨率为0.2 ps的脉冲波形,理论上需要5 TSPS的采样率才能实现。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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