{"title":"Triggers, data flow and the synchronization between the Auger surface detector and the AMIGA underground muon counters","authors":"Z. Szadkowski","doi":"10.1109/TNS.2011.2142194","DOIUrl":null,"url":null,"abstract":"The aim of the AMIGA project (Auger Muons and Infill for the Ground Array) is an investigation of Extensive Air Showers at energies lower than by standard Auger array, where the transition from galactic to extragalactic sources is expected. The Auger array is enlarged by a relatively small dedicated area of surface detectors with nearby buried underground muon counters at half or less the standard 1.5 km grid. Lowering the Auger energy threshold by more than one order of magnitude allows a precise measurement of the cosmic ray spectrum in the very interesting regions of the second knee and the ankle. The paper describes the working principle of the Master/Slave (standard Auger surface detector/the underground muon counters) synchronous data acquisition, general triggering and the extraction of data corresponding to the real events from underground storage buffers applied in two prototypes: A) with 12.5 ns resolution (80 MHz) built from 4 segments: standard Auger Front End Board (FEB) and Surface Single Board Computer (SSBC) (on the surface) and the Digital Board with the FPGA and the Microcontroller Board (underground), B) with 4-times higher: 3.125 ns resolution (320 MHz) built with two segments only: new surface Front End Board supported by the NIOS® processor and CycloneIII™ Starter Kit board underground, working also with NIOS® virtual processor, which replaces the external TI µC, which in meantime became obsolete. The system with the NIOS® processors can remotely modify and update: the AHDL firmware creating the hardware FPGA net structure responsible for the fast DAQ, the internal structure of the NIOS® (resources and peripherals) and the NIOS® firmware (C code) responsible for software data management. With the standard µC, the µC firmware was fixed and could not be updated remotely. The 80 MHz prototype passed laboratory tests with real scintillators. The 320 MHz prototype (still being optimized) is considered as the ultimate AMIGA design.","PeriodicalId":345878,"journal":{"name":"2010 17th IEEE-NPSS Real Time Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 17th IEEE-NPSS Real Time Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TNS.2011.2142194","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
The aim of the AMIGA project (Auger Muons and Infill for the Ground Array) is an investigation of Extensive Air Showers at energies lower than by standard Auger array, where the transition from galactic to extragalactic sources is expected. The Auger array is enlarged by a relatively small dedicated area of surface detectors with nearby buried underground muon counters at half or less the standard 1.5 km grid. Lowering the Auger energy threshold by more than one order of magnitude allows a precise measurement of the cosmic ray spectrum in the very interesting regions of the second knee and the ankle. The paper describes the working principle of the Master/Slave (standard Auger surface detector/the underground muon counters) synchronous data acquisition, general triggering and the extraction of data corresponding to the real events from underground storage buffers applied in two prototypes: A) with 12.5 ns resolution (80 MHz) built from 4 segments: standard Auger Front End Board (FEB) and Surface Single Board Computer (SSBC) (on the surface) and the Digital Board with the FPGA and the Microcontroller Board (underground), B) with 4-times higher: 3.125 ns resolution (320 MHz) built with two segments only: new surface Front End Board supported by the NIOS® processor and CycloneIII™ Starter Kit board underground, working also with NIOS® virtual processor, which replaces the external TI µC, which in meantime became obsolete. The system with the NIOS® processors can remotely modify and update: the AHDL firmware creating the hardware FPGA net structure responsible for the fast DAQ, the internal structure of the NIOS® (resources and peripherals) and the NIOS® firmware (C code) responsible for software data management. With the standard µC, the µC firmware was fixed and could not be updated remotely. The 80 MHz prototype passed laboratory tests with real scintillators. The 320 MHz prototype (still being optimized) is considered as the ultimate AMIGA design.