High speed PLL frequency synthesizer for mobile communications

A. Kajiwara, M. Nakagawa
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引用次数: 2

Abstract

A novel phase locked loop (PLL) frequency synthesizer with high switching speed is proposed. The experimental and theoretical results are given. The PLL synthesizer proposed is composed entirely of digital signal processors except for a voltage controlled oscillator (VCO). The VCO control signal is derived by the subtraction of the linear reference phase and the feedback phase. Therefore, it does not need the bandlimited loop filter which limits the ability of the loop to switch rapidly. The experimental results show that it can provide a switching time as short as 0.1 ms, which is 10/sup 2/-10/sup 3/ times higher than conventional PLL synthesizers, and spurs of less than -65 dBc/Hz.<>
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用于移动通信的高速锁相环频率合成器
提出了一种具有高开关速度的锁相环频率合成器。给出了实验和理论结果。所提出的锁相环合成器除压控振荡器(VCO)外全部由数字信号处理器组成。通过线性参考相位和反馈相位的相减得到压控振荡器的控制信号。因此,它不需要限制环路快速切换能力的带限环路滤波器。实验结果表明,它的开关时间短至0.1 ms,是传统锁相环合成器的10/sup 2/-10/sup 3/倍,杂散小于-65 dBc/Hz。
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