An optimized reversible signed comparator

Abstract

The comparator has become one of the most embossed component in electronic circuit design. They work on a simple logic wherein the two inputs fed are compared and accordingly outputs are produced such as greater or lesser or equal. Comparators have proved their significance in the fields of digital communications, encryption devices, ADC circuits etc. This paper proposes a design of a signed comparator using reversible logic gates. Reversible logic these days has been one of the most compelling field of research due to its pragmatic advantages such as low power consumption, reduced heat loss, lower number of garbage outputs and decreased quantum cost. The proposed design works well with all the combinations of signed numbers which makes it distinguishable among the other pre-proposed designs. The proposed design also aims at optimizing the design parameters such as quantum cost, garbage outputs and ancillary inputs. However the design has proved to have a better performance compared to the existing design.