Low-Complexity Parallel Systolic Architectures for Computing Multiplication and Squaring over FG(2^m)

Abstract

Recently, cryptographic applications based on finite fields have attracted much interest. This paper presents a unified systolic multiplier under the method of the multiply-by-alpha2 and the folded technique. This circuit can be suited for implementing both multiplication and squaring in GF(2m). The results show that our proposed multiplier saves about 75% space complexity and 50% latency as compared to the traditional multipliers proposed by Yeh et al. and Wang-Lin. Also, the proposed squarer saves about 45% space complexity as compared to the traditional squarer presented by Guo and Wang.