Mapping algorithms onto the TUT cellular array processor

J. Viitanen, T. Korpiharju, J. Takala, H. Kiminkinen
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引用次数: 4

Abstract

The Tampere University of Technology Cellular Array (TUTCA) processor array is based on a dynamically configurable logic cell array. It is intended for efficient implementation of the direct mapping dataflow principle with a self-timed, distributed control structure. The architecture of the processor, principles of mapping algorithms on it, and the compiler of the dataflow language are described. The language used for programming is a slightly modified version of DFL. The main features of DFL, the parser, the array processing, the graph structure generated by DFL, and the performance and exploitation of parallelism are considered.<>
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映射算法到TUT蜂窝式阵列处理器
坦佩雷科技大学的细胞阵列(TUTCA)处理器阵列是基于一个动态可配置的逻辑细胞阵列。它旨在有效地实现具有自定时、分布式控制结构的直接映射数据流原理。介绍了处理器的体系结构、映射算法的原理以及数据流语言的编译器。用于编程的语言是DFL的稍微修改版本。讨论了DFL的主要特点、解析器、数组处理、DFL生成的图结构以及并行性的性能和利用。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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Design of run-time fault-tolerant arrays of self-checking processing elements Domain flow and streaming architectures A fault-tolerant two-dimensional sorting network Algorithmic mapping of neural network models onto parallel SIMD machines The bit-serial systolic back-projection engine (BSSBPE)
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