Design of variable length code decoder for AVS based on FPGA

Abstract

Aiming at the AVS standard which is the audio and video standard of China, an optimized variable length code decoder is proposed for the AVS standard. The design uses an innovative circular shifter to improve decoding parallelism. It optimizes the VLC tables and uses combinational look-up table circuit to avoid memory access. Self-adaptive pipeline technique is adopted to improve decoding speed. The design has been described in Verilog HDL at RTL level, simulated and tested in ModelSim, synthesized and validated on the FPGA chip. The simulation and verification indicates that the decoder can reach the requirement of AVS video decoding.