Towards a tool for implementing delay-free ECC in embedded memories

Abstract

The reliability of modern Integrated Circuits is affected by nanometric scaling. In many modern designs embedded memories occupy the largest part of the die and are designed as tight as allowed by the process. So they are more prone to failures than other circuits. Error correcting codes (ECC) are a convenient mean for protecting memories against failures. A major drawback of ECC is the speed penalty induced by the encoding and decoding circuits. In [5], we propose an architecture eliminating ECC delays in both read and write paths. However, this previous work does not describe a generic set of rules enabling inserting the delay-free ECC in any design. In this paper, we present the key points of an algorithm and a related tool automating its implementation.