Layout-level Vulnerability Ranking from Electromagnetic Fault Injection

Abstract

Trusted microelectronics are increasingly threatened by fault injection attacks through a variety of physical means. Electromagnetic fault injection (EMFI) is a low-cost but effective approach to induce parasitic currents on a victim chip. To address the gap between logic fault principle and silicon EMFI mechanism, a layout-level simulation methodology to identify physical vulnerabilities of the victim chip is needed. In this paper, a fast numerical inductance solver is proposed to characterize the location-dependent coupling effects between EM field signal and on-chip wires. To validate the simulation accuracy, the result from our solver is calibrated with a 3D EM field solver to achieve great correlation. Leveraging parallel computing techniques, our tile-based simulation on a large design has been demonstrated as an accurate and effective ranking of EMFI vulnerabilities of the victim chip.