Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor Platform

2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation Pub Date : 2007-07-16 DOI:10.1109/ICSAMOS.2007.4285736

H. Blume, Jörg von Livonius, Lisa Rotenberg, T. Noll, Harald Bothe, J. Brakensiek

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引用次数: 7

Abstract

In this contribution, the potential of parallelized software that implements algorithms of digital signal processing on a multicore processor platform is analyzed. For this purpose various digital signal processing tasks have been implemented on a prototyping platform i.e. an ARM MPCore featuring four ARM 11 processor cores. In order to analyze the effect of parallelization on the resulting performance-power ratio, influencing parameters like e.g. the number of issued program threads have been studied. For paralllelization issues the OpenMP programming model has been used which can be efficiently applied on C- level. In order to elaborate power efficient code also a functional and instruction level power model of the MPCore has been derived which features a high estimation accuracy. Using this power model and exploiting the capabilities of OpenMP a variety of exemplary tasks could be efficiently parallelized. The general efficiency potential of parallelization for multiprocessor architectures can be assembled.

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MPCore多处理器平台上并行化实现的性能和功耗分析

在这篇贡献中，分析了在多核处理器平台上实现数字信号处理算法的并行软件的潜力。为此，在原型平台上实现了各种数字信号处理任务，即具有四个ARM 11处理器内核的ARM MPCore。为了分析并行化对产生的性能-功率比的影响，研究了诸如发出的程序线程数等影响参数。对于并行问题，采用了OpenMP编程模型，该模型可以有效地应用于C级。为了编写高效节能的代码，本文还推导了一个具有较高估计精度的功能级和指令级的MPCore功耗模型。使用这个强大的模型并利用OpenMP的功能，可以有效地并行化各种示例任务。多处理器架构的并行化的一般效率潜力可以组装。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation

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