Efficient Countermeasures against Fault Attacks for 3DES Crypto Engine in Bank IC Card

Abstract

As bank IC cards with chips are widely used nowadays, the security of them becomes increasingly important. Fault attack, which aims to inject fault into the chip during the calculation, is a serious threat to the information security of the chip. Thus considerable countermeasures are involved to meet the overall requirements and facilitate the intended application for bank IC cards. In this paper, countermeasures against fault attacks for 3DES (Triple Data Encryption Algorithm) which is one of the widely used block ciphers in the bank IC cards are designed and implemented. Those countermeasures in our paper are based on the symmetry structure of DES block and we try to dig the efficiency in it. The basic countermeasure reduces the time latency from 100% to 1/n × 100% for n round block cipher. On the basis of this, an optimized countermeasure lowers the redundancy rate from 1/4 to 1/16. Another optimization reduces the area cost of duplication than the second method, which has the same latency. The countermeasures are designed for the 3DES algorithm in RTL level, implemented and verified in FPGA board. The fault attack platform successfully injected clock glitch into the DES engine and demonstrated the validity of the countermeasure. Over 1000 3DES calculations are tested and the successful detection rate is 100%.